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We implemented a LED display controller which receives multiple gray-level images in Verilog and then uses EDA tools to generate the layout.
An exploration of algorithms to achieve range-preserving determinization.
A lane tracking system integrating motors, camera, VGA and FPGA.
Published in IEEE/ACM Asia and South Pacific Design Automation Conference, 2020
We designed and implemented a timing-aware dummy fill insertion Engine by estimation and mitigation of the equivalent capacitance caused by the dummy fills (Best Paper Nominee)
Recommended citation: Sheng-Jung Yu, Chen-Chien Kao, Chia-Han Huang and Iris Hui-Ju Jiang. "Equivalent Capacitance Guided Dummy Fill Insertion," in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, 2020.
Published in , 2020
This paper is about the Codesign of Network Structure and Physical Routing for Optical Networks-On-Chips System (Submitted).
Published in , 2020
This paper is about the Wavelength-Division-Multiplexing-Aware Clustering Algorithm For On-Chip Optical Routing (Submitted).
Published:
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Undergraduate course, University 1, Department, 2014
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Workshop, University 1, Department, 2015
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